Static Random Access Memory (SRAM) cells comprise an increasing portion of modern very large scale integrated (VLSI) circuits due to their low activity factor, which leads to low active power density, and ease of design. A conventional SRAM cell 10 is illustrated in FIG. 1. One issue with the conventional SRAM cell 10 is that current through pull-down transistors M1 or M3 when reading a logic “0” from output node N1 or N2, respectively, reduces the Static Noise Margin (SNM) of the conventional SRAM cell 10 during the read operation. More specifically, a read operation is performed by pre-charging bit lines BL and BLN to a high voltage level and the write line WL is pulled high in order to turn on access transistors M5 and M6. If a logic “0” is stored at output node N2, pull-up transistor M2 is off and pull-down transistor M1 is on. Due to the voltage division across transistors M1 and M5, the voltage at the output node N2 rises above VSS. This rise in voltage at the output node N2 decreases the SNM during the read operation.
The rise in voltage at the output node N2 when reading a logic “0” is determined by the cell ratio of the gate size of the pull-down transistor M1 to that of the access transistor M5. The higher the cell ratio, the smaller the voltage drop across the pull-down transistor M1 and the greater the SNM of the cell. Thus, the pull-down transistor M1 must be stronger than the access transistor M5 so that a logic “0” stored at the output node N2 is not pulled high during a read operation. Similarly, the pull-down transistor M3 must be stronger than the access transistor M6 so that a logic “0” stored at output node N1 is not pulled high during a read operation. However, there is a conflicting restraint that the pull-up transistors M2 and M4 be weaker than the access transistors M5 and M6 in order to ensure write-ability, thereby constraining the design space for the conventional SRAM cell 10.
Stability is further complicated by modern highly scaled processes. More specifically, increasing mismatch due to processing and lithographic variation and even random dopant fluctuations (RDF) has made SRAM stability problematic in highly scaled processes. In addition, the source voltage VDD needed to ensure stability in modern highly scaled processes is becoming increasingly problematic since the PMOS source voltage VDD must be decreased as the size of the transistors M1-M6 in the conventional SRAM cell 10 is decreased in order to prevent destruction of the transistors M1-M6 by applying an excessive voltage across the gate oxide of the corresponding gates.
Leakage power or current is also an issue with the conventional SRAM cell 10. FIG. 2 illustrates transistor leakage components in a Metal Oxide Semiconductor (MOS) transistor. The leakage components include a drain to source leakage component (IOFF), a direct band-to-band tunneling leakage component through the gate oxide (IGATE), a gate induced drain leakage component (IGIDL), and a direct band-to-band tunneling leakage component at the transistor drain to body, or bulk, interface (IZENER). As the size of the transistor decreases, the source voltage VDD applied to the transistor and thus the threshold voltage (Vt) of the transistor must also decrease. The reduction in the threshold voltage (Vt) results in an exponential increase in IOFF, and the reduction in the power supply voltage VDD results in an exponential decrease of the leakage components IGATE, IGIDL, and IZENER. However, a conventional 6-T SRAM cell suffers degraded read static noise margin with reduced VDD. This currently limits the allowable VDD reduction in practice.
Thus, there is a need for a SRAM cell having high stability and low leakage.